Online repair manual

Parts List:
R1,R3,R4 = 10K 1/4W
R2=100K 1/4W
CY1,CY2 = 0.22uF Polyester
C1,C2 = 10uF/25V Electrolytic
IC1 = uA741A Single Op-Amp Ic + 8 Pin Ic Socket
3 Pin Male & Female Connector x 2
2 Pin Male & Female Connector x 1
PCB as in required size 4.5 cm x 3.4 cm

This active audio audio system use three TDA2052 chips and 5 speakers ( one woofer, two tweeters and two midranges ) .For this TDA2052 active audio system we need dual 20 volts power supply and five volts supply for the stand by function.To the input of the every audio IC chip is placed an audio filter for filtering the audio signal for used speakers ( low pass for woofer , high pass for midranges and tweeters )

Active Audio System Circuit Diagram

The subwoofer plays the 20 to 300 Hz frequency range, while the remaining 300 Hz to 20KHz are sent to two separate channels with stereo effect.If one of the amplifier is affected by clipping distortion the others amplifiers are not affected .

The electronic circuit provides a visual time 9 second delay using ten LED before control by closing a 12 Vdc relay. That the reset switch has closed, IC 4017 decade counter will be reset to zero count which illuminates the LED driven from pin 3. IC 555 timer output at pin 3 will be high and the voltage at pins 6 and 2 of the timer will be a little less than the lower trigger point, or about 3 Vdc.

9 Sec Timer with LED Indication and Control Relay Circuit Schematic
 

That time the switch is opened, the transistor in parallel with the timing capacitor (22uF) is shut off allowing the capacitor to begin charging and the IC 555 timer circuit to produce an approximate one second clock signal to the decade counter. The counter advances on each positive going change at pin 14 and is enabled with pin 13 terminated low. When the 9th count is reached, pin 11 and 13 will be high, stopping the counter and energizing the relay. Longer delay times can be obtained with most capacitor or most resistor at pins 2 and 6 of the IC 555 timer.

The generator circuit was designed to produce alternating square pulses with vibrations in different parts of the circuit.

4027 – a dual JK flip flop that has independent clock, set, and reset inputs for each flip flop used in toggle, register, and control functions due to its features such as capability of driving two low power TTL loads, logic edge clocked flip flop design, logic swing independent of fanout, toggle rate of 3 MHz at 5 Vdc, supply voltage range of 3 V to 6 V, protection of diodes on all inputs, noise immunity, and quiescent current of 2 nA at 5 Vdc. 4001 – a quad 2-input NOR gate integrated circuit, generally characterized by small fluctuation in voltage supply, very high impedance, outputs that can sink and source, one output can drive up to 50 inputs, high speed gate propagation time, high frequency, and low power consumption.

Alternating Square Pulse Generator Circuit Diagram

BC550 – an NPN general purpose transistor with low current and low voltage used for low noise stages in audio frequency equipment

The generator functions without distortion when it reaches 100 KHz. The square pulses are produced when the selector switch S1 is turned ON, which matches the output of Q3 at pin 7. The 5V pulse line is applied to J1 input, the signal is fed to T-flip flop IC1A through S2 which creates pulses indicated at half of the duration time where pin 2 handles the division of pulse frequency. The pulses are applied to IC2 pin 14 and IC3A input. IC2 acts as decimal counter with decode outputs where each entry produces HIGH on one of the outputs. From the initial pulse entry, the output of Q1 becomes HIGH while others are LOW. The second pulse entry causes HIGH output on Q2, and third entry applies on Q3. The same operation occurs for the succeeding pulse line entry, since the counter checks the number of pulses that passes the generator output.

The generator output stage is considered on levels where the driving stage of Q2 creates positive output voltage and the saturation of Q 3 in the cutoff region. Through the potentiometer, the signal is applied in the output of J2. Using the gates of IC3B-C-D, the sine wave or triangular wave can be changed to square pulses in the circuit input. The conversion is directly made from the command of S2. The switching can also be done by DIP switch S2. A suitable power supply or two NiCd batteries can maintain the circuit with the stabilization of voltage achieved by two Zener diodes.

R1-10= 10Kohm
R2= 47Kohm
R3= 22Kohm
R4-5= 18Kohm
R6-7= 4.7Kohm
R8= 1.2Kohm
R10= 100Kohm
R11-13= 470 ohm
R12= 1.5Kohm RV1= 1.2Kohm linear pot.
C1= 15pF ceramic
C2-3= 10nF 63V MKT
C4-5= 470uF 16V
C6= 1uF 63V MKT
D1-2= 5.1V 0.5W zener
D3-4= 1N4148
Q1-2= BC560C
Q3= BC550C IC1= 4027
IC2= 4027
IC3= 4001B
S1= switch DIL 10S
S2-3= 2X2 mini switch
LD1= LED
BATT= 9V Battery NiCd

The generation of square pulses can bring about plenty of usages by adjusting the input in digital circuits and controlling the frequencies of amplifiers, loudspeakers, rooms of hearings, and others. One popular application is in the camera flash temporal profile where square pulses act as a heating source in the photoflash technique. The amount of light emitted by an electronic flash is controlled by the shunted output of a pulse generator known as tailbiters where longer pulses are made with the biting off the tail of the impulse.

This is a circuit of Power-Fail and Low-Line Signals. This circuit is used to warn the processor when the power failure or a brownout is occurs. The processor will enter a power-down routine, when either of those signals interrupts the processor. Back up important data prior to the POR placing the processor in reset and cease its current  activities are things that the processor do when enter the routine. Here is the circuit.Power-fail comparator is used to create a power-fail signal by monitoring the unregulated DC voltage. The regulator powers both supervisor circuit and the processor by using the the unregulated DC voltage.

Power-Failure and Low-Line Signals Schematic


 The regulator’s output capacitor retains its output voltage, so the unregulated voltage drops before the regulator’s voltage. And also, we can know drop in the regulator’s voltage. The processor can enter its power-down routine prior to being reset, if the power supply voltage were to drop low enough because of Detecting the regulator’s voltage drop.A supervisor provides a low-line signal, which goes active whenever the monitored power supply drops to a level slightly above the reset threshold so the processor can still receive warning of an imminent power failure when there is no access to the unregulated voltage.

To cause the POR to issue a reset, the processor warned that the power-supply voltage may decrease enough by the low-line signal. To anticipate the POR generating a reset, the processor backs up important data because of power failure  or a brownout.